Design and Architectural Optimization of Viterbi Decoder

نویسندگان

  • Yue Hu
  • Feng Liu
چکیده

This report reviews previous work on Viterbi algorithm and decoder design. Our work is based on a (2, 1, 4) architecture with hard decision. Different hardware architectures are applied to Add-Compare-Select unit (ACS) and the entire system, and the performances on energy, area, and speed are compared. Keywords-convolutional code; maximum likelihood decoding; Viterbi algorithm

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Hardware Optimazation of Viterbi Decoder

This paper describes the design and optimization of Viterbi Decoder used for (2,1,3) convolution code. It first introduces the basic principle of Viterbi Algorithm, then describes the basic circuit architecture of the Viterbi Decoder. Then it compares several different architecture and circuit optimization method, which emphasize on aspects such as throughput, power and memory consumption. Fina...

متن کامل

High Speed ACSU Architecture for Viterbi Decoder Using T-Algorithm

In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating Talgorithm. Through optimization at both algorithm level and architecture level, the new architecture greatly shortens the long critical path introduced by the conventional T-algorithm. The design example provided in this work demonstrates more than twice improvement in clock speed wi...

متن کامل

A Design Environment for High-Throughput Low-Power Dedicated Signal Processing Systems

A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined dataflow graph and floorplan description drives automatic layout generation with commercial CAD tools. Automatic characterization of layout improves system-level estimates. Simplified physical design methodologies for low supply voltages a...

متن کامل

A 500-Mb/s Soft-Output Viterbi Decoder

Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted...

متن کامل

Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for the standards GSM/GPRS/EDGE, in order to reduce power consumption and die area as desired for cellular applications. To this end, the hardware implementation of a channel shortening pre-filter combined with a delayed decision-feedback sequence estimator (DFSE) for channel e...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2012